Exposure mask with double patterning technology and method for fabricating semiconductor device using the same

ABSTRACT

An exposure mask for forming a G-type active region with a double patterning technology includes a bar shaped first light-blocking pattern to define an I-type active region, and an island shaped second light-blocking pattern to define a bit line contact region. The first light-blocking pattern and the second light-blocking pattern are arranged alternately.

This application is based upon and claims the benefit of priority toKorean Patent Application No. 10-2007-0065280, filed on Jun. 29, 2007,the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The invention relates to an exposure process. More particularly, theinvention relates to an exposure mask and a method for fabricating asemiconductor device using the same.

BACKGROUND

When a general active region of a DRAM is formed, the area of the centerportion of the active region, that serves as a bit line contact region,is increased in order to increase a current amount and reduce a contactresistance with a bit line. The active region having an increased centerportion is called a G-type active region.

FIG. 1 is a layout of an exposure mask for I-type active region. Anexposure mask 100 includes a bar shaped light-blocking pattern 110 todefine an I-type active region.

FIGS. 2 a and 2 b are top-views illustrating a double patterning processof forming an I-type active region of a semiconductor device. A firsthard mask layer 214 is formed over a semiconductor substrate 200. Alithography process is performed using exposure mask 100 of FIG. 1 toform a second hard mask pattern 220. An exposing process is performedusing exposure mask 100 of FIG. 1 to form a photoresist pattern 225which is disposed between second hard mask patterns 220. First hard masklayer 214 is etched using second hard mask pattern 220 and photoresistpattern 225 as a mask to form a first hard mask pattern 230 that definesan I-type active region.

In order to form a hard mask pattern defining a G-type active region, anoptical proximity correction (“OPC”) process is performed so that agiven thickness of the center portion of light-blocking pattern 110 ofFIG. 1 is protruded toward both sides in a minor axis direction of theG-type active region. In the OPC process, a margin for protruding thecenter portion is insufficient to increase a bit line contact resistanceand reduce the current amount, thereby degrading characteristics of thedevice.

SUMMARY

Embodiments of the invention are directed to an exposure process with adouble patterning technology. According to an embodiment of theinvention, the exposure process includes an exposure mask for forming aG-type active region. The exposure mask includes a bar shaped firstlight-blocking pattern and an island shaped second light-blockingpattern to secure an OPC process margin and reduce a bit line contactresistance, thereby improving characteristics of the device.

According to an embodiment consistent with the invention, an exposuremask for forming a G-type active region with a double patterningtechnology includes a bar shaped first light-blocking pattern to definean I-type active region. The exposure mask includes an island shapedsecond light-blocking pattern to define a bit line contact region. Thesecond light-blocking pattern is separated from the first light-blockingpattern.

According to an embodiment consistent with the invention, a method forfabricating a semiconductor device includes forming a first hard masklayer over a semiconductor substrate. A second hard mask layer is formedover the first hard mask layer. The second hard mask layer is etchedusing a photolithography process with the exposure mask of the abovedescribed exposure mask to form a second hard mask pattern. Aphotoresist pattern is formed using an exposing process with the shiftedexposure mask. The photoresist pattern overlaps the second hard maskpattern. The first hard mask layer is etched using the second hard maskpattern and the photoresist pattern as a mask to form a first hard maskpattern. The first hard mask pattern defines a G-type active region. Thesecond hard mask pattern and the photoresist pattern are removed. Thesemiconductor substrate is etched using the second hard mask pattern toform a trench for device isolation.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a layout of an exposure mask for forming an I-type activeregion of a semiconductor device;

FIGS. 2 a and 2 b are top-views illustrating a double patterning processof forming an I-type active region of a semiconductor device;

FIG. 3 is a layout of an exposure mask for forming a G-type activeregion of a semiconductor device according to an embodiment consistentwith the invention;

FIGS. 4 a and 4 b are top-views illustrating a double patterning processof forming a G-type active region of a semiconductor device according toan embodiment consistent with the invention;

FIG. 5 is a layout of an exposure mask for forming a G-type activeregion of a semiconductor device according to another embodimentconsistent with the invention; and

FIGS. 6 a and 6 b are top-views illustrating a double patterning processof forming a G-type active region of a semiconductor device according toanother embodiment consistent with the invention.

DETAILED DESCRIPTION

The invention relates to an exposure process employing a doublepatterning technology (“DPT”). In one embodiment of the invention, theexposure process includes an exposure mask employing DPT.

FIG. 3 is a layout of an exposure mask for forming a G-type activeregion of a semiconductor device according to an embodiment consistentwith the invention. An exposure mask 300 includes a bar shapedlight-blocking pattern 310 to define an I-type active region. A centerportion (that is, a bit line contact region) of the light-blockingpattern 310 has a line-width larger than that of the other activeregion.

FIGS. 4 a and 4 b are top-views illustrating a double patterning processof forming a G-type active region of a semiconductor device according toan embodiment consistent with the invention. A first hard mask layer 414and a second hard mask layer (not shown) are sequentially formed over asemiconductor substrate 402. A lithography process is performed usingexposure mask 300 of FIG. 3 to form a second hard mask pattern 420 todefine a G-type active region. A photoresist film (not shown) is formedover semiconductor substrate 402 and second hard mask pattern 420.

Exposure mask 300 of FIG. 3 is shifted at a given distance, and anexposing process is performed to form a photoresist pattern 425 betweensecond hard mask patterns 420. First hard mask layer 414 is etched usingsecond hard mask pattern 420 and photoresist pattern 425 as a mask toform a first hard mask pattern 430. Second hard mask pattern 420 andphotoresist pattern 425 are removed. Semiconductor substrate 402 isetched using first hard mask pattern 430 as a mask to form a trench fordevice isolation that defines a G-type active region.

FIG. 5 is a layout of an exposure mask for forming a G-type activeregion of a semiconductor device according to another embodimentconsistent with the invention. An exposure mask 500 defines a G-typeactive region. Exposure mask 500 includes a bar shaped firstlight-blocking pattern 510 a to define an I-type active region. Exposuremask 500 includes an island shaped second light-blocking pattern 510 bto define a bit line contact region.

First light-blocking pattern 510 a and second light-blocking pattern 510b are arranged alternately. The arrangement of first light-blockingpattern 510 a and second light-blocking pattern 510 b is not limitedherein. A line-width of second light-blocking pattern 510 b in its majoraxis is larger than that of first light-blocking pattern 510 a in itsminor axis.

A center portion of first light-blocking pattern 510 a corresponds to abit line contact region. A given thickness of the center portion offirst light-blocking pattern 510 a is protruded out in its minor axis.First light-blocking pattern 510 a is shaped in rectangle, cruciform ordiamond. The shape of first light-blocking pattern 510 a is not limitedherein.

Since bar shaped first light-blocking pattern 510 a and island shapedsecond light-blocking pattern 510 b are separated, a space where apattern to define a bit line contact region is formed is located betweenfour bar shaped first light-blocking patterns 510 a. As a result, it ispossible to secure a sufficient space where an OPC process is performed.

FIGS. 6 a and 6 b are top-views illustrating a method of fabricating asemiconductor device to form a G-type active region of a semiconductordevice according to another embodiment consistent with the invention.FIGS. 6 a and 6 b illustrate a double patterning process of forming aG-type active region with exposure mask 500 of FIG. 5. A first hard masklayer 614 and a second hard mask layer (not shown) are formed over asemiconductor substrate 602. A lithography process is performed usingexposure mask 500 of FIG. 5 to form a second hard mask pattern 620.Second hard mask pattern 620 includes a bar shaped first pattern 620 ato define an I-type active region. Second hard mask pattern 620 includesa second pattern 620 b to define a bit line contact region.

A line-width of second pattern 620 b in its major axis is larger thanthat of first pattern 620 a in its minor axis. First pattern 620 a andsecond pattern 620 b are arranged alternately. A center portion of firstpattern 620 a includes a protrusion part protruded from first pattern620 a in its minor axis by a given thickness.

Referring to FIG. 6 a(ii), a photoresist film (not shown) is formed overa semiconductor substrate 602 including second hard mask pattern 620. Anexposing process is performed using exposure mask 500 of FIG. 5 to forma photoresist pattern 625 overlapping second hard mask pattern 620. Theexposure process is performed after exposure mask 500 of FIG. 5 isshifted to a given distance.

Photoresist pattern 625 includes an island shaped third pattern 625 a todefine a bit line contact region. Photoresist pattern 625 includes a barshaped fourth pattern 625 b to define an I-type active region. Thirdpattern 625 a is overlapped with first pattern 620 a of second hard maskpattern 620. Fourth pattern 625 b is overlapped with second pattern 620b of second hard mask pattern 620.

Referring to FIG. 6 b, first hard mask layer 614 is etched usingphotoresist pattern 625 and second hard mask pattern 620 to form a firsthard mask pattern 630 to define a G-type active region. Photoresistpattern 625 and second hard mask pattern 620 are removed.

A portion of the semiconductor substrate 602 is etched using first hardmask pattern 630 as an etching mask to form a trench for deviceisolation (not shown). The trench for device isolation is filled with adevice isolation insulating film to form a device isolation structure todefine a G-type active region. A process of forming a gate and a processof forming a bit line are performed to obtain a semiconductor device.

As described above, according to an embodiment consistent with theinvention, a G-type active region is formed using a double patterningtechnology with an exposure mask to secure a sufficient bit line contactregion, reduce a bit line contact resistance and increase a currentamount, thereby improving characteristics of the device.

Although a number of illustrative embodiments consistent with theinvention have been described, it should be understood that numerousother modifications and embodiments can be devised by those skilled inthe art that will fall within the spirit and scope of the principles ofthis disclosure. More particularly, a number of variations andmodifications are possible in the component parts and/or arrangements ofthe subject combination arrangement within the scope of the disclosure,the drawings and the appended claims. In addition to variations andmodifications in the component parts and/or arrangements, alternativeuses will also be apparent to those skilled in the art.

1. An exposure mask for forming a G-type active region with a doublepatterning technology, the exposure mask comprising: a bar shaped firstlight-blocking pattern to define an I-type active region; and an islandshaped second light-blocking pattern to define a bit line contactregion, the second light-blocking pattern separated from the firstlight-blocking pattern.
 2. The exposure mask of claim 1, wherein thefirst light-blocking pattern and the second light-blocking pattern arealternately arranged.
 3. The exposure mask of claim 1, wherein a centerportion of the first light-blocking pattern is protruded in a miner axisthereof.
 4. The exposure mask of claim 1, wherein the firstlight-blocking pattern is shaped in rectangle, cruciform or diamond. 5.A method for fabricating a semiconductor device, the method comprising:forming a first hard mask layer over a semiconductor substrate; forminga second hard mask layer over the first hard mask layer; etching thesecond hard mask layer using a photolithography process with theexposure mask of claim 1 to form a second hard mask pattern; forming aphotoresist pattern using an exposing process with the shifted exposuremask of claim 1, the photoresist pattern overlapping the second hardmask pattern; etching the first hard mask layer using the second hardmask pattern and the photoresist pattern as a mask to form a first hardmask pattern defining a G-type active region; removing the second hardmask pattern and the photoresist pattern; and etching the semiconductorsubstrate using the first hard mask pattern to form a trench for deviceisolation.
 6. The method of claim 5, wherein the second hard maskpattern comprises a bar shaped first pattern having a protruding portionover a center of the first pattern and an island shaped second pattern,the first pattern and the second pattern arranged alternately along ax-direction, a y-direction or both directions.
 7. The method of claim 6,wherein the photoresist pattern comprises an island shaped third patternand a bar shaped fourth pattern having a protruding portion over acenter of the fourth pattern, the third pattern and the fourth patternarranged alternately.
 8. The method of claim 7, wherein the thirdpattern overlaps the protruding portion of the first pattern.
 9. Themethod of claim 7, wherein the second pattern overlaps the protrudingportion of the fourth pattern.